At the HPC-AI Advisory Council UK conference, AMD revealed new details about its Zen 3 and Zen 4 architectures, along with a roadmap that gives us the timeline and some key specs for its next-gen EPYC Milan and Genoa lines of EPYC data center chips. The presentation was uploaded to YouTube and then taken down in rather quick fashion, likely because the company wasn’t ready to divulge these key details yet. We snagged a copy of the video before it was taken down and have some new details of AMD’s future plans.
AMD’s revolutionary Zen microarchitecture introduced the world to mass-produced chiplet-based processors that enable the company to use the same underlying design across both consumer and enterprise chips. Any changes to the company’s architecture will filter out to all of its new client and enterprise chips, meaning these changes will likely come to the vaunted Ryzen lineup of chips in the future.
But when? AMD presented a roadmap outlining the arrival of the Milan chips, which feature Zen 3 cores, entering production in Q3 2020. That means the company is executing its plan of providing yearly updates to its architecture. The company also noted that it has already taped out the chips and is sampling them to customers.
The new Milan chips will feature the 7nm+ node, a refreshed version of the current node with higher performance. They also feature the same maximum of 64 cores as the current-gen Rome models and drop into the same SP3 socket, meaning they are backward compatible with existing platforms. They’ll also come with the same support for eight channels of DDR4 and PCIe 4.0 and respect the base 120-225W TDP envelope, though it’s logical to expect higher-TDP variants like the 7H12 are also in the works. The chips also have two threads per core, silencing the rather dubious rumors that AMD would switch to four threads per core (SMT4) as we see with some competing chips.
The next-gen Milan chips still feature the same nine-die arrangement as the current-gen Rome models, with eight compute die and one I/O die, along with eight cores assigned to each compute chiplet. The largely unchanged specifications, at least in key areas, implies Milan is merely a “Tock”-equivalent, or just a move to the second-gen of the 7nm node (7nm+).
However, AMD also disclosed that the company had made a significant alteration to the cache alignments inside the chip, which indicates that there is significant work being done under the hood to improve instruction per cycle (IPC) throughput and reduce latency, both of which are key focus areas for AMD as it evolves its architecture. AMD currently splits its chiplets into two four-core Compute Complexes (CCX), each armed with 16MB of L3 cache. For Milan, that changes to eight cores connected to a unified 32MB slice of L3 cache, which should eliminate a layer of latency within the compute die.
Much of the success of a design hinges on its ability to feed the execution cores with data (feeding the beast, as it were), and significance improvements in these areas will bring along an increase in IPC, giving us more performance gains than we would normally expect from a mere refresh generation. Pair that with improved frequency from a faster and more mature variant of the 7nm process and AMD could provide some exceptional gen-on-gen performance gains, regardless if core counts remain static.
That feeds into AMD’s assertion that it would continue to provide groundbreaking new levels of performance with each iteration of its microarchitecture, breaking the mold of incremental performance updates that we’ve become accustomed to during Intel’s decade of dominance.
AMD continues onward with its next-next-gen Genoa architecture that is already in the “definition phase.” The chip will drop into a new SP5 socket and land somewhere in the 2021 time frame. The company says Genoa will come with “new memory,” likely meaning DDR5. We’re sure AMD is also considering a jump to PCIe 5.0.
Intel isn’t sitting idly by, though, with purported plans to be on the Sapphire Rapids chips in Q1 2021, with a rumored 8-channel DDR5 design and support for PCIe 5.0. It’s clear that the two companies will continue to trade blows for years to come in an ever more competitive market.